Innosilicon SD4.0 PHY supports both UHS-II and Legacy SD interface. The UHS-II standard is targeted for mobile, portable applications and home applications, provides enhanced data rate, while maintaining low power and low EMI. The Legacy SD IOs supports traditional operation speed like DS, HS, DDR50 and SDR50/104 for providing the features of backwards compatibility.
Innosilicon UHS-II PHY interface achieves a peak speed of 3.12Gbps. It consists of at least two lanes based on differential signaling lines. Each lane provides up to 156MB/sec.The direction of both lanes can be configured as two opposite ways (FD mode), or same way (2L-HD mode). In 2L-HD mode case, the interface speed is doubled to 312MB/sec. It is also possible to have more than two Lanes, 3 or 4 Lanes for increasing system speed.
InnosiliconSD4.0 PHY includes high-speed low-delay multiple-voltage legacy SD IOs compatible with multiple bus modes in Legacy SD, and UHS-I, which are Default Speed, High Speed, UHS50, UHS104. CMD19 (Tuning CMD) is supported by the PHY in UHS-I mode, with DLL integrated inside PHY to provide clock with adjustable phases.
The PHY uses sub-LVDS signaling consisting of one pair each for transmit, receive (D0, D1 Lanes) and an additional reference clock (RCLK Lane). D0 and D1 Lanes are used for differential transmission between Host and Device which are dedicated to UHS-II interface only, and are separate for signals of legacy SD interface. The D0 and D1 signals are encoded by 8b/10b code before transmission, and decoded by 10b/8b after receiving. RCLK is transmitted from Host to Device, and operates at 1/15th or 1/30th of the data transfer speed. This differential clock operates between 26MHz to 52 MHz and is carried over the legacy SD lines DAT0, and DAT1.
The PHY also provides loopback path for testability purposes, and used for Devices in order to perform data bypassing in ring topology. The loopback paths have the same clocking scheme as TX and RX Lanes in FD mode, for both forward and backward loopback.
Functions and Features
Dedicated data lanes support high speed interface up to 3.12GT/s
Differential low voltage signaling with DC coupling
Compatible with Legacy SD interface
Low voltage, low power consumption, low EMI
Low frequency reference Clock (RCLK) with embedded PLL
Two types of duplex mode: FD mode, 2L-HD mode (Optional)
8b/10b encoding and 10b/8b decoding
high-speed low-delay multiple-voltage legacy SD IOembedded
UHSI Tuning CMD supported
ESD protection circuitincluded
Legacy UHS-1 and Voltage-Switching Features
Support for UHS50 and UHS104 cards with the following speeds, frequencies, and voltages, as appropriate for each card:
Default Speed Mode- 25Mhz, 3.3v
High Speed mode – 50Mhz, 3.3v
SDR12 – 25Mhz,1.8v
SDR25 – 50Mhz, 1.8v
SDR50 – 100Mhz, 1.8v
SDR104 – 208Mhz, 1.8v
DDR50 – 50Mhz, 1.8v
Voltage switching between 1.8v and 3.3v.
UHS-II PHY features:
SD BUS interface mode supports DS, HS, SDR12, SDR25, SDR50, SDR104, DDR50 UHS-II interface mode supports FD156 and HD312
Compliant with SD Specifications Part 1 UHS-II Addendum v1
Supports data rate between 390 Mbps to 1.56 Gbps per lane
Supports peak interface speed of 3.12 Gbps in Half-duplex mode; 1.56 Gbps in Full-duplex mode
Sub-LVDS differential PHY signaling
Low frequency differential reference clock (1/15th or 1/30th) of data rate
Supports Spread Spectrum clocking to reduce EMI
Low power consumption
Simple integration process
Available options include:
Test chips and test boards
FPGA integration support
Chip level integration
Mobile, portable applications and home applications
Digital video and SLC cameras