The INNOSILICON MIPI M-PHY transceiver is fully compatible with V1-00-00 specifications. It supports both master and slave roles in HS Gear 1~3 and LS operation. The M-PHY uses the MIPI standard M-PORTs Protocol Interface to simplify controller integration and supports DigRFv4, SSIC, and UniPro MIPI protocols.
The architecture is customizable and allows support from 1 to 4 lanes for increased throughput. It is designed with ease of integration in mind. The PHY is small, low power and contains all I/Os including primary and secondary ESD.
Efficient production testing is assured through built in BIST, multiple loop back modes and Boundary scan support.
Easily ported into any technology
Compliant with MIPI M-PHY V1-00-00 standard
Supports HS mode Gear1～3
Supports M-PHY Type-II system
Supports the reference frequencies： 19.2/26/38.4/52MHz
Up to 5.8 Gb/s data transfer rate per lane
TX drivers are programmable for amplitude, slew rate and de-emphasis to ensure a 200mV to 800mV signal window as appropriate.
On-die terminations are auto-calibrated during handshake for both value and matching
Incorporates spread spectrum clocking (SSC) for all interface implementations with control for spectrum offset, range shape and skew rate
Advanced Rx equalization
Embedded primary and secondary ESD
Production test supported with BIST, loop back and boundary scan
Loop back has 7 different configurations to support production testing, debug and in-system testing.
Provided deliverables support all major EDA tools and contain a detailed integration guide
Low power consumption
Simple integration process
Available options include
lTest chips and test boards
lFPGA integration support
lChip level integration